1/3/2024 0 Comments Mesi cache coherence![]() ![]() ![]() Assume that all the words in both caches are clean. Assume that both processors use write-back write-update cache coherency, and a block size of one word. Assume that all the words in both caches are clean.ĪSSIGNMENT #3 1) Count the number of transactions on the bus for the following sequence of activities involving shared data. Fill the following table for the following sequence of instructions: Time instant Operation Content of the directory for X 1 Processor 0 – read X 2 Processor 5 – read X 3 Processor 0 – writes to Xħ size of one word. Assume that directory for address X contained all 0s at the beginning. QUESTION #3 MIDTERM b) Consider a multiprocessing system with 8 processors that have their local caches and they are connected to the main memory: If Full Map Directory cache coherence protocol is implemented, what is the number of bits per directory? Why? 1 bit is used per processor, so that the number of bits is 8 If Limited Directory cache coherence protocol with only two pointers is implemented, what is the number of bits per directory? Why? Log28=3, the number of bits per pointer is 3 and the total number of bits is 6 Assume that Full Map Directory cache coherence protocol with Centralized Directory Invalidate is implemented. P0 reads a’Ħ 1 bit is used per processor, so that the number of bits is 8 P3 writes back a’ P0’s cache P1’s cache P2’s cache P3’s cache P0 reads a E I P1 reads a S P2 reads a P3 writes a M 3. P0’s cache P1’s cache P2’s cache P3’s cache P0 reads a E I P1 reads a P2 reads a P3 writes a P0 reads aģ P0’s cache P1’s cache P2’s cache P3’s cache P0 reads a E I P1 reads a S P2 reads a P3 writes a P1 reads a P2 reads aĤ P0’s cache P1’s cache P2’s cache P3’s cache P0 reads a E I P1 reads a S P2 reads a P3 writes a M P3 writes a 1. P0’s cache P1’s cache P2’s cache P3’s cache P0 reads a P1 reads a P2 reads a P3 writes a MESI cache coherence protocolĢ Initial assumption: a invalid in all caches Each processor starts out with the line containing a invalid in their cache. For the following sequence of memory references, show the state of the line containing the variable a in each processor’s cache after each reference is resolved. QUESTION #3 MIDTERM a) A four-processor shared-memory system implements the MESI protocol for the cache coherence. ![]()
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